I obtained several of these boards from eBay. They came with no manual and no ROMs. This is a double-sided PC board which makes it much easier to trace the wiring and generate a schematic. I have this partially complete.
This board has a bit-banged serial port using the 8085 RIM/SIM commands and the timer in the 8155 chip. I have a version of my monitor for this configuration once I figure out the RAM and 8155 addresses.
1146 MST 22 January 2012
I have returned to this board for awhile. I had an offer from Herb Johnson to trade a known working CPU board for one or two multibus proto boards. Since I have never powered or tested any of the 4 Zendex processors I have, now is the time to do that. I will use the hp 1650B Logic Analyzer to help me figure out the RAM and I/O addressing. I know where the ROM socket that is addressed at 0H is located. I can write some simple 8085 code to exercise the RAM and I/O address lines and see the results on the logic analyzer. I will start with designing an 8085 probe for the logic analyzer. This will be done just like I did the 8086 probe discussed on the Test Equipment and Adapters on the Main page.
1600 MST 12 February 2012
I will need to build an 8085 Probe to debug this board. With no Hardware Reference Manual available, I will need to figure out the RAM and I/O decoding another way. The partial diagram helps, so I know where the ROM addressed at 0h is located on the board. I can write some simple software to exercise certain memory and I/O addresses and use the logic analyzer to show which addresses enable which chips or iSBX sockets. Work on this continues.
1224 MST 13 February 2012
I have made good progress on this board. I have a nearly complete set of hand drawn schematics that are here. Newer schematics are farther down the page. I have been able to read both the memory and I/O decoder PROMs. I have hand-coded source for these PROMs (I/O located here and memory here). I have some notes on the SBC here. I will add to the notes as I find more out about the SBC.
I had to build a cable to connect the onbaord bit-banged serial port to my PC to test the first version of the monitor. The cable connects to the large connector on the top right hand side of the picture above. I used a connector pulled from an old XT power supply to connect to a DE-9M connector. This cable is shown below.
1608 MST 20 February 2012
I have completed the schematics of the Zendex ZX-80/05 SBC. The complete diagrams are located here.
I have got the 8085 probe on one of these SBCs. I put a erased EPROM in U39. The 0xFF is an RST7 instruction on the 8085. The machine fetches the first 0xFF from location 0x0000 after the reset. It runs the instruction then does not get a ready signal from the memory decoder. This is similar to the error I got initially on the Intel iSBC 86/30 board. I have more debugging to do!
1354 MST 1 March 2012
I pulled the ROM out of the socket, but left it enabled. Because of the multiplexed address and data bus on the 8085 processor, it fetches the low address byte as the instruction. The state lines are mapped on the first page to the signals monitored by that bit.
A listing of the logic analyzer output with comments on the right side is located here. This run begins at 0000h and continues until the processor tries to access offboard memory. The processor fails to get a READY signal and continues to try the read forever. Each state of the 8085 is displayed on one line.
Since the address that fails to return a READY signal is located in the ROM map, I placed a jumper for ROM 1 to enable it. If configured for 2764s, this shouls be the ROM that holds addresses 2000-3FFFH. The logic analyzer was the same as above. I moved that jumper to the ROM 2 position, and the analyzer captured many more instructions until address 2C30H was selected for a write. Ready again never returned. A listing of this logic analyzer output is located here. It is odd that address 2C2FH returns a READY signal, but address 2C30H does not! I need to reevaluate my decode of the memory decoder PROM.
The failure to get a READY signal for an offboard address is probably misconfiguration of the jumpers for the 8219 bus arbiter or a misconfiguration of the jumpers on the 64K byte RAM board. This board works correctly with the Intel iSBC 80/10 processor as conficured.
1339 MST 3 March 2012
I have completed the schematic diagrams of the board. I went back and found I had errors in the memory decoder PROM source that is on the site. I have corrected that file and the notes on the Zendex-80/05. Currently, the address decoder is working as it is supposed to. I had the switch positions of S1 reversed! I have made some minor corrections to the schematic and will scan it in tomorrow.
1806 MST 3 March 2012
I have an almost complete manual for this board here. I will continue to try and figure out why this board will not get an XACK signal from the iSBC 064 RAM board. To this end, I have begun to build a Multibus probe for the HP1650B Logic Analyzer. WIth that and some programming, I should be able to figure out the failure mode.
1918 MST 13 April 2013